Programmable integrated circuit devices such as field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), system on a chip (SoC) and the like, may be configured to perform various functions. These programmable devices perform a configuration by reading configuration data from a program memory (e.g., read only memory or flash memory) and copying the configuration data to state registers (e.g., configuration registers) of the programmable device. Functional blocks (e.g., which perform user-defined logic functions), I/O blocks (e.g., which configure input/output blocks interfacing to external devices), and/or signal routing resources (e.g., which connect the functional blocks to the I/O blocks), for example, may be established this way.
A central processing unit (CPU) and/or a controller of the programmable device may be used to perform such configurations during a reset and/or runtime. However, only one configuration bit pattern is stored at runtime. Thus, the configuration may not be changed during runtime. Moreover, the configuration involves moving the configuration data from the program memory to the configuration registers, which is a time and resource consuming process. As the number of functions being performed increases, the amount of memory sufficient to configure the registers increases, thereby consuming valuable resources and increasing costs.